1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device having a macro cell structure with a cell-base well contact.
2. Description of the Prior Art
FIG. 8 is a layout diagram of a prior art semiconductor integrated circuit device having a macro cell structure with a well contact, for example, disclosed in JP-A-04/267553. FIG. 9 is an enlarged view in left-part in the semiconductor integrated circuit device of FIG. 8. FIG. 10 is a sectional view taken along II-IIxe2x80x2 line of FIG. 9.
In the drawings, reference numerals 101a, 101b each denote well contacts, numeral 2 denotes a diffusion region, numeral 3 denotes a rectangular cell frame of a macro cell, numeral 11 denotes a p-type semiconductor substrate such as Si, numeral 12 denotes a p-well, numeral 13 denotes an n-well, numeral 14 denotes an oxide film, numerals 115a, 115b each denote a p+ diffusion region, numerals 116a, 116b each denote an n+ diffusion region, numerals 17a, 17b each denote a contact which connects a ground wiring 18a and a power supply line 18b to the p+ diffusion region 115a and the n+ diffusion region 116b, respectively, numerals 18a, 18b denote the ground wiring for supplying ground voltage GND (0V), and the power supply wiring for supplying power supply voltage VDD (1.8V) respectively, both of which are made of metal such as aluminum, symbol A designates an area having a large contact effect, and symbol B designates an area having a small contact effect. Here, the respective combinations of the diffusion regions 115a, 115b with the contacts 17a, 17b are defined as the well contacts 101a, 101b. 
In general, when a cell-base semiconductor integrated circuit device has a CMOS structure, the n-well 13 is enhanced to the power supply voltage VDD, and the p-well 12 is set to the ground voltage GND so as to prevent latchup. Therefore, the power supply wiring 18b is electrically connected to the n-well region 13 through the n+ diffused region 116b, while the power supply wiring 18a is electrically connected to the p-well region 12 through the p+ diffused region 115a. However, the presence of the latchup means that in semiconductor integrated circuit devices having a CMOS structure and so on, a phenomenon is caused in which the ON state of a parasitic thyristor formed by parasitic bipolar PNP, NPN transistors nearly causes a short state between power supply and ground. This results not only in abnormal operation but also element malfunction.
The layout diagram of FIG. 8 shows the diffusion region 2 in which transistors are constituted in the cell frame 3 of the macro cell, and the well contacts 101a, 101b. In recent years, to achieve a high density in cell bases, there has been a tendency to fabricate macro cells of a smaller size as a circuit unit. For this reason, the well contacts 101a, 101b described above have been arranged between the diffusion regions 2 in which transistors are constituted.
The operation will be next described.
On the side of ground voltage supplying, the ground voltage GND is provided in the p+ diffusion region 115a via the contact 17a, and the ground voltage 0V is provided in the p-type semiconductor substrate 11 via the p-well 12. On the other hand, on the side of power supply voltage supplying, the power supply voltage VDD is provided in the n+ diffusion region 116b from the power supply wiring 18b via the contact 17b, to be transferred in the n-well region 13. However, from the n-well 13 to the p-type semiconductor substrate 11, the power supply voltage VDD is provided in the former, while the ground voltage GND is provided in the latter, which leads to a xe2x80x9creverse-biasedxe2x80x9d condition to diodes in which no current flows.
Incidentally, JP-A-08/222640 discloses a semiconductor integrated circuit device having an improved latchup resistant cell. In addition, JP-A-07/78949 discloses a semiconductor integrated circuit in which a silicide structure is provided in the upper surface of a diffusion region, and is used for power and ground regions.
Since a semiconductor integrated circuit device having a macro cell structure has the above structure in the prior art as described above, there is a problem that since the well contacts 101a, 101b cannot be formed on the whole surface of the macro cell, the region A having a large well contact effect occurs at a place near the well contacts 101a, 101b, while the region B having a small well contact effect occurs at a place far from the well contacts 101a, 101b. 
The present invention has been made to solve the above-described problem, and it is an object of the present invention to obtain a semiconductor integrated device having an improved latchup resistant macro cell structure such that even when a macro cell with just partially taken contacts is used, the well contact effect spreads over a wider area, e.g., the whole macro cell.
According to the present invention, a macro cell structure comprises: a first diffusion region having the minimum permissible width, formed apart at least by the minimum inter-diffusion distance from both left and right side ends in upper and lower sides of a rectangular macro cell region, and formed in the vicinity of both upper and lower ends of the macro cell region; and a second diffusion region in which a well contact is formed, wherein the first diffusion region is electrically connected with the second diffusion region. Thus, the well contact effect provided in the second diffusion region spreads over the first diffusion region electrically connected therewith, thereby improving latchup resistance over a wider range of the macro cell.
According to the present invention, a macro cell structure comprises: a first diffusion region having the minimum permissible width, formed from at least one of both left and right side ends in upper and lower sides of a rectangular macro cell region, and formed in the vicinity of both upper and lower ends of the rectangular macro cell region; and a second diffusion region in which a well contact is formed, wherein the first diffusion region is electrically connected with the second diffusion region. Thus, even if adjoining macro cells have no well contacts at the left and right sides of the above macro cell, the adjoining macro cells are brought in contact and electrically connected with each other, thereby receiving the well contact effect. Therefore, since the well contact effect may be rendered to not only macro cells having well contacts but also macro cells having no well contacts, the latchup resistance of the whole semiconductor integrated circuit device may be improved.
According to the present invention, a second macro cell structure having no well contacts includes: a third diffusion region having a minimum permissible width, formed from at least one of both left and right side ends in upper and lower sides of the rectangular macro cell region, and formed in the vicinity of both upper and lower ends of the macro cell region, wherein when the macro cell structure is disposed at at least any one of left and right sides of the second macro cell structure, the first diffusion region is electrically connected with the third diffusion region in upper side and/or lower side of the macro cell region. Thus, the well contact effect may be also rendered to the macro cell having no well contacts, thereby improving latchup resistance over the whole semiconductor integrated circuit device.
According to the present invention, a macro cell structure comprises: a fourth diffusion region having half or more of the minimum permissible width, formed from at least one of both left and right side ends in upper and lower sides of the rectangular macro cell region, and formed in the vicinity of both upper and lower ends of the macro cell region; and a second diffusion region in which a well contact is formed, wherein the first diffusion region is electrically connected with the second diffusion region. Thus, the micro cell structures are vertically brought in contact and electrically connected with each other, so that a width of the combined diffusion region satisfies the minimum permissive width. With this manner, the well contact effect may be rendered to a wider range of the macro cell, and further the macro cell may be shrunk since a poly-wiring region such as polycrystalline silicon in the macro cell widens, resulting in a high density of the semiconductor integrated circuit device in addition to the above-mentioned improvement of the latchup resistance.
According to the present invention, a plurality of the macro cell structures each are provided with fifth diffusion regions as follows: the fourth diffusion regions are electrically connected with each other at upper and lower sides of said macro cell region, the fifth diffusion region satisfying the minimum permissible width, thereby resulting in the improvement of the latchup resistance and high-density of the device.
According to the present invention, the fifth diffusion regions are electrically connected with each other at left and right sides of the macro cell region. Thus, the well contact effect spreads throughout not only the relating macro cell but also the whole semiconductor integrated circuit device, thereby resulting in the improvement of the latchup resistance and high density of the device.
According to the present invention, the plurality of macro cell structures include a macro cell structure having no well contacts. Thus, the well contact effect spreads over the macro cell having no well contacts, thereby resulting in improvement of the latchup resistance and high density of the whole device likewise.
According to the present invention, at least one of the first to fifth diffusion regions is made of a salicide structure of a refractory metal to reduce electric resistance of these surface layers. Thus, the well contact effect may spread over the whole device more effectively through the diffusion region connected with the well contact. In addition, since the minimum permissible width itself may be reduced, an area of the macro cell may also be reduced, thereby resulting in improvement of the latchup resistance and high density of the device.
According to the present invention, since the minimum permissible width of the first, third, fourth and fifth diffusion regions is not allowed to be disposed with a well contact, resulting in a high density of the device due to wider poly-wiring regions in the macro cell.